This invention relates in general to the field of error correction in a computer, and in particular to error correction in conjunction with object reuse protection in a digital computer.
Error detection and correction coding is designed so that fault-free encoded data satisfies certain mathematical properties. If the encoded data fails to satisfy these properties, one or more bits of the encoded data are in error. If the code incorporates sufficient additional information, it may be possible to identify which bit or bits are in error and require correction. Often hardware is designed to automatically make these corrections as the data is accessed. However, if there are more bits in error than the code can correct, an "uncorrectable error" occurs. Error correction codes are often designed so that they can detect many of these uncorrectable errors so that hardware can abort data access by causing an interrupt or by halting processing. But, if too many bits are in error, an uncorrectable error can masquerade as error-free data or as a correctable error. The probability of such uncorrectable errors is reduced by selecting an encoding that detects the most likely error cases.
Computer security needs very often accompany error detection and correction needs. Patent application Ser. No. 07/878,280 entitled "Memory Tagging for Object Reuse Protection", addressed the problem of prevention of unauthorized access to reused memory. The solution to the object reuse protection problem described in patent application Ser. No. 07/878,280 relies on information stored in additional hardware to provide protection against unauthorized access to data remaining in memory when memory objects are reused.
It would be advantageous to provide an error detection and correction method and apparatus which could be used in mainframe computers, minicomputers, microcomputers, computer workstations and embedded communications equipment in conjunction with the above-referenced object reuse protection method and apparatus. It would be particularly advantageous to provide combined object reuse protection with error-detection and/or error-correction coding using any off-the-shelf CPU. The combination object reuse and data error detection/correction method would be especially desirable in systems that require some measure of fault detection or fault tolerance. It would also be desirable if the object reuse and data error detection/correction method and apparatus would provide combined error detection/correction with object reuse protection for nearly the same cost as providing either of the two features alone.